Case Studies
Specialization
Home / Markets / Sample-Rate Converter

Sample-Rate Converter

Audio interface converter based on FPGA Spartan-3E (XC3S250E) is implemented in the media-player. Three I2S streams are separated from the data format packet 256 bit wide stream (generated by the Processor Blackfin ADSP-BF533 for AD1836) for the subsequent transformation to S/PDIF. Multiplexed commutation between incoming and outgoing streams is possible. The incoming I2S stream is forced for the oversampling to 48 kHz.

FPGA architecture layout of sample-rate converter

Sample-Rate Converter is implemented as two CIC-filters. The incoming stream of any frequency (44.1 kHz, 48 kHz, 96 kHz) is M times interpolated to high frequency (50 MHz) and is N times thinned by the decimator. M and N coefficients are selected by the detector based on input frequency so that output system frequency is 48 kHz.

FPGA also implements the accompanying logic for ADSP-BF533 processor: keyboard debounce, IR-commands detector, processing of signals coming from optic encoder (volume control), frame buffer for LCD-monitor, S/PDIF-transmitter (CS8427) control logic and «glue-logic» for connection of NAND-Flash and Wi-Fi modules.

Detail architecture layout of sample-rate converter

Specifications

FPGA-type Spartan-3E 250 (XC3S250E)
Outside IP-cores were not applied
Interfaces SPORT (BlackFin audio)
IP cores
  • I2S
  • SPI
  • glue logic
  • sample-rate converter
Peculiarities SNR > 80 db
Design tools ISE 9.2, Modelsim XE, Synplify 8.6
Lead time 1,5 months

Download PDF - 108Kb