Video Processing Unit: Engineering Process

Customer

A Russian company, one of Russia’s leading companies in development and practical use of unmanned space exploration systems.

Objective

Development of a software/hardware platform for exploring the capabilities of a video compression algorithm developed by the customer. Engineering of two system environment options for hardware and software integration of a video compression algorithm supplied by the customer.

Hardware

Uncompressed bmp data were received through a Gigabit Ethernet interface for processing. A codec system environment was implemented for data reception, RAM storage and transfer for further processing. Two implementation versions of a video compression algorithm were developed and tested - fully software implementation and implementation in which part of transformations were performed on the FPGA programmable logic. Based on the compression performance data, recommendations were developed for the customer to optimize the algorithms.

To solve this task, the ML507 demonstration platform by Xilinx was used. The system is based on the FPGA XC5VFX70T-1-FF1136, on which all major nodes and components are implemented.

The embedded MCU PPC440 processor operating at 400 MHz is used as the control processor. The system PLB bus frequency is 100 MHz.

The FPGA implements a number of specialized EDK modules for the system operation. See Figure 1.

Figure 1. Structural diagram of the system

• The ppc440_0_apu_fpu_virtex5 module is used for floating-point operations. The bus frequency is 133 MHz.It is connected to the processor through a specialized FCB bus.
• The Hard_Ethernet_MAC module is used for implementing LAN 10/100/1000 Mbit. This module is controlled through the PLB bus. A special port in the processor, SDMA, is used for data transfer. Data are sent from the SDMA port through an internal memory arbiter to the MPCM memory controller port.
• The SysACE_CompactFlash module is connected to the system for recording or reading data from the CompactFlash external card. Currently it is not used.
• The FLASH module is an external NOP FLASH controller. The NOP FLASH includes the U-boot primary bootloader, Linux and the FPGA configuration binary file. This solution helps reconfigure the FPGA firmware as well as Linux system files using the U-boot over the LAN.
• The RS232_Uart_1 module is designed for the control function as well as control through the COM port.
• The xps_timer_1 module is a timer controller. It is designed for generating time tags for the system. It is controlled by the processor though the PLB bus.
• The xps_timebase_wdt_1 module is a watchdog timer controller. It is designed for CPU reset when it freezes. Currently it is not used.
• The IIC_EEPROM module is an I2C bus controller. Currently it is used for recording and reading system variables for U-boot from external EEPROM.
• The LEDs_8Bit module is an input/output controller (GPIO). It is used for output to control LED indication. Currently it is not used. It may be used to indicate the status of the system and the modules. It is controlled by the processor through the PLB bus.
• The xps_intc_0 module is an interrupt controller.
• The xps_dvi_in_0 module is designed for converting video data and loading it into the system memory. See a more detailed description below.

The xps_dvi_in_0 module consists of four major nodes operating at different frequencies. See Figure 2.

Figure 2. Xps_dvi_in_0 structural diagram

The Dvi Input unit receives video data in RGB format over the parallel bus from the TFP403. The maximum pixel clock frequency is 100 MHz. The current operating frequency is <80 MHz (it depends on the video card operation mode). It uses progressive scan.

The functions of the Dvi Input unit include converting video data from RGB (4:4:4) to YCbCr (4:2:2).

The received and converted data are then sent to the fifo_bank unit for further loading into the system memory.

The Control NPI unit is responsible for loading data into the system memory. Data are loaded separately by frames and components.

The PLB Slave unit is used for connecting with the PLB bus to control and manage the module.

Software Platform

ELDK (Embedded Linux Development Kit) by Xilinx was used for software development. It is designed for Linux kernel assembly for the PowerPC architecture, Linux applications and the U-Boot bootloader.

Version 2.6.33 from Xilinx’s official repository was used as the Linux kernel for the project.

A special driver was developed for access to video data received through the xps_dvi_in_0 module. The driver provides applications with a V4L2 interface (Video for Linux 2).

Also, a set of scripts and utilities was developed to receive video frames and test individual elements of the compression algorithm.

The developed software architecture is shown in Figure 3.

Figure 3. Software architecture

The system performance was measured in different modes of the processor operation.

A set of documents with a step-by-step description of the software development and assembly process in the ELDK environment was prepared for the customer.

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